Hi, my name is Shaunak Sarlashkar

A Computer Engineering Student at Purdue University with interests in AI/ML, Embedded Systems, Computer Architecture, and Digital Design.

Email: me[at]shaunak[dot]dev

Experience

Incoming Firmware Engineering Intern @ Xylem

May 2026 - Aug 2026

Firmware & Embedded Systems Intern @ Xerox (formerly Lexmark)

May 2025 - Aug 2025

• Enhanced firmware image-processing path by improving reliability within a Yocto-based Embedded Linux Stack.
• Benchmarked embedded platforms with lmbench to characterize CPU, memory, and I/O behavior.
• Collaborated with firmware & image halftoning teams to validate behavior on target hardware.
• Debugged system-level issues in the lmbench suite to accurately characterize kernel-space interactions and performance metrics.

Embedded LinuxYoctoC++Systems Debugging

Undergraduate Teaching Assistant @ Purdue University

Aug 2025 - Present

• Support graduate & undergraduate level ML and optimization assignments for ECE 570 & ECE 473 (Artificial Intelligence).
• Assist students on debugging PyTorch implementations and understand reinforcement learning pipelines.
• Grade exams and programming projects to ensure correctness classwide.

PyTorchMachine LearningReinforcement Learning

Projects

Kernel-Lint: LLM-Powered Linux Patch Reviewer

WIPApril 2026 - Present

Developed an LLM-powered CLI tool to automate the pre-review process for Linux kernel patches. Provides semantic analysis on locking rationale and subsystem-specific conventions (e.g., Memory Management) before LKML submission. Complements checkpatch.pl by identifying high-level architectural issues.
Source: github.com/shaunaks-tech/kernel-lint

PythonAnthropic APIPydanticLinux Kernel

RISC-V 32-bit Pipelined Processor

Engineered a 5-stage pipelined RV32I processor with full hazard detection and forwarding logic. Implemented a 2-way set associative data cache and a dedicated instruction cache to minimize memory-access stalls and improve IPC. Verified architectural performance and correctness through comprehensive SystemVerilog testbenches.

SystemVerilogComputer ArchitectureRISC-V

SystemVerilog Systolic Array Matrix Multiplier

Designed an AI Accelerator featuring an 8x8 Systolic Array, AHB interface, and SRAM buffer. Developed a controller FSM to manage data hazards, reducing inference latency to under 75 cycles. Validated architectural correctness through Questasim waveform analysis and testbench simulations.

SystemVerilogRTLASIC Design

Car Safety Detection System

Engineered a hazard detection system on STM32F0, integrating ultrasonic sensors with UART telemetry for real-time distance tracking. Developed a non-blocking firmware architecture using ISRs for sensor polling and SPI with Circular DMA to drive a live OLED dashboard.

STM32 / ARMEmbedded CDMA/SPI

Vim Tutor Web App

A React-based website that teaches Vim interactively through a LeetCode-style interface. Features a terminal emulator, lesson progression, and glassmorphism UI.
Visit at: vimdojo.app
Source: github.com/shaunaks-tech/learnvim

ReactTypeScript